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Semiconductor
SD6830
4BIT MICROCONTROLLER
1. Description
SD6830 is a remote control transmitter, consists of the optimized 4-bit CPU with ROM and RAM. It contains power-on reset, watchdog timer and carrier frequency generator. The SD6830 provide a various carrier frequency for encoding output of key matrix and has built-in transistor to drive infrared LED. The SD6830 is supported with a software development tool, which allows code development in a PC environment. It allows the user to simulate the SD6830 on an instruction level.
2. Features
* Number of basic instructions ------------------------------------- 45 * Instruction cycle time (one word instruction) At Fsys=480KHz ---------------------------------------- 16.67uS At Fsys=455kHz ---------------------------------------- 17.58uS * Memory size ROM --------------------------------------------------- 1024 x 8 Bits RAM ------------------------------------------------------ 32 x 4 Bits * Input ports (D0 ~ D3, E0 ~ E3 : with pull-up resistor) * Output ports (C, G, K, F0 ~ F7) * Carrier frequency generator Fsys/12 (1/2 duty), Fsys/12 (1/3 duty), Fsys/12 (1/4 duty), Fsys/8 (1/2 duty), Fsys/8 (1/4 duty), Fsys/11 (4/11 duty), No carrier * Watchdog Timer * Built-in power on reset * Single power supply ------------------------------------------------ 1.8V ~ 3.6V * Power dissipation (stop mode , VDD = 3V) ----------------------- Less than 3uW * Package ------------------------------------------------------------- 20/24 DIP, 20/24 SOP * Low-power system applications such as an infrared remote controller * MASK OPTION 1. Divide ratio of the oscillator frequency 2. Whether connected infrared LED driver or not * Descriptions of this spec sheet assume that the SD6830 include driver for infrared LED.
3. Ordering Information
Type NO. SD6830P-option SD6830-option SD6830P-option SD6830-option Marking SD6830P-option SD6830-option SD6830P-option SD6830-option Package Code DIP20 SOP20 DIP24 SOP24
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4. Block Diagram
VSS 1 OSCIN 2 OSC OSCOUT3 Watchdog Timer Z Carrier Frequency Generator 3 Port C 23 C/REM Test Control 4 3 G4 Port G 4 A 4 D0 5 D1 6 D2 7 D3 8 Port D 4 4 4 STACK 10 PC E0 9 E1 10 E2 11 E3 12 4 4 Key Input Detector OSC Start/Stop Control Port E 8 4 SF Instruction Decoder 10 CY ALU 20 F0 19 F1 18 F2 Port F 17 F3 16 F4 15 F5 14 F6 13 F7 4 B Port K 21 K 22 TEST 24 VDD
Reset Control 4
H RAM L 4
ROM
Figure 4-1 Block Diagram of the SD6830
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5. PIN Assignment and Description 5.1 PIN Assignment for 24PINS( DIP24, SOP24)
VSS OSCIN OSCOUT G D0 D1 D2 D3 E0 E1 E2 E3 1 2 3 4 5 6 7 8 9 10 11 12 OUTLINE 24 PIN DMC6830 24 23 22 21 20 19 VDD C/REM TEST K F0 F1 F2 F3 F4 F5 F6 F7
SD 6830
SD6830
18 17 16 15 14 13
Figure 5-1. Pin Assignment of 24 Pins
5.2 PIN Description for 24 PINS
Symbol
VDD VSS TEST OSCin OSCout C/REM D0 - D3 E0 - E3 F0 - F7 G K
Pin No.
24 1 22 2 3 23 5~8 9 ~ 12 20 ~ 13 4 21
I /O
INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT OUTPUT Power Supply Ground
Functions
I/O Type
Input for test ( Normally connected to VSS ) Input for oscillating Output for oscillating 1-Bit output for remote transmission 4-Bit input for key sense ( with pull-up resistor ) 4-Bit input for key sense ( with pull-up resistor ) 1-Bit individual output for key scan 1-Bit output 1-Bit output B A A C D D
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5.3 PIN Assignment for 20PINS( DIP20, SOP20)
VSS OSCIN OSCOUT D0 D1 D2 D3 E0 E1 F6
1 2 3 4 5 6 7 8 9 10 OUTLINE 20 PIN
20 19 18 17
VDD C/REM TEST K F0 F1 F2 F3 F4 F5
SD 6830 DMC6830
SD6830
16 15 14 13 12 11
Figure 5-3. Pin Assignment of 20Pin
5.4 PIN Description for 20 PINS
Symbol
VDD VSS TEST OSCin OSCout C/REM D0 - D3 E0 - E1 F0 - F6 K
Pin No.
20 1 18 2 3 19 4~7 8~9 16 ~ 10 17
I /O
INPUT INPUT OUTPUT OUTPUT INPUT INPUT OUTPUT OUTPUT Power Supply Ground
Functions
I/O Type
Input for test ( Normally connected to VSS ) Input for oscillating Output for oscillating 1-Bit output for remote transmission 4-Bit input for key scan ( with pull-up resistor ) 2-Bit input for key scan ( with pull-up resistor ) 1-Bit individual output for key scan 1-Bit output B A A C D
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5.5 I/O CIRCUIT SCHEMATICS

VDD
30 150
PIN
DATA

VSS

Note If STOP mode specified, the the TYPE C output becomes "L" state and the output B output becomes NOTE: :If STOP mode isis specified, TYPE C output becomes "L" state and the TYPE B TYPE becomes floating floating state, the TYPE D output maintains previous state. state state, the TYPE D output maintains previous
Figure 5-5. I/O Circuit Schematics
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6. Basic Function Block 6.1 Program Counter (PC)
Program counter is used to indicate the address of the next instruction to be executed. The 10-bit program counter consists of two registers, PCH(4-bit) and PCL (6-bit). This is a polynomial counter.
6.2 Program Memory (ROM)
Program memory is used to store user-specified program. This consists of a 1024 x 8-bit. It is organized in 16 pages and each page is 64 bytes long. For page-in addressing, all instructions excluding JMPL and CALL can be executed by page. In order to execute jump or call in page, JMP or CAL is suitable. For page-to-page addressing, JMPL or CALL must be used.
PROGRAM COUNTER PCHFigure 6-1. Program Memory Map (6-BIT) (4-BIT) PCL
PAGE 0 000h 0 1 2 3
PAGE 15 60 61 62 63 0 RESET ADDRESS 1 2 3
60 PROGRAM MEMORY
61
62
63
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6.3 Data Memory (RAM)
Data memory is used to store various type of processing data. This consists of a 32-nibble, which is organized into two files of 16 nibbles each. RAM addressing is indirectly implemented by a two registers; H, L. It's upper 1-bit register (H) selects one of two files and its lower 4-bit register (L) selects one of 16 nibbles in the selected file.
REG H (1-bit)
REG L ( 4-bit )
FILE 0 FILE 1 0 1 2 0 3 1 2 3 4 Lower 3-bit PORT F
F0 F1 F2 F3 F4 F5
12
13
14 12
15 13 14 15
F6 F7
DATA MEMORY
Figure 6-2. Data Memory Map
6.4 Stack Register (SK)
Stack register is used to store return address and provide a particularly mechanism for transferring control between programs. Two level hardware push/pop stacks are manipulated by CAL, CALL, and RET instructions. CAL/CALL instructions push the current program counter value, incremented by "1", into stack level 1. Stack level 1 is automatically pushed to level 2. If more than two subsequent CAL/CALL are executed, only the most recent two return addresses are stored. RET instruction load the contents of stack level 1 into the program counter while stack level 2 gets copied into level 1. If more than two subsequent RET are executed, the stack will be filled with the address previously stored in level 2.
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6.5 Arithmetic and Logic Unit (ALU)
This unit is used to perform arithmetic and logical operations such as addition, comparison, and bit manipulation.
6.6 Carry Flag (CY)
The carry flag contains the carry generated by the arithmetic and logical unit immediately after an operation. The set carry (SETB CY) and clear carry (CLRB CY) instructions allow direct access for setting and clearing this flag.
6.7 Skip Flag (SF)
The skip flag is a 1-bit register, which enables programs to conditionally skip an instruction. All instructions are executed when this flag is The following instructions affect the skip flag , the program executes NOP instruction and resets SF to "0". Then program execution proceeds.
Instructions
Arithmetic ADD n INC L IF0 @HL.b IF0 CY IFEQU @HL IFEQU n STA @HL+ XCH @HL+
Set conditions of SF
If carry occurs (L) = 0 M[HL].b = 0 (CY) = 0 (A) = M[HL].b (A) = n (L) = 0 (L) = 0
Compare
Data Transfer
The instructions, which doesn t affect the skip flag but have a skip condition, are as follows.
Instructions
Data Transfer Bit Manipulate LDA n LDL n SETB H CLRB H
Skip conditions
If it is continuous, skip next same instruction. If it is continuous, skip next same instruction. If SETB H or CLRB H are continuous, skip next SETB H or CLRB H instruction.
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6.8 Registers
Register A Register A, called the accumulator, plays a central role, is used to store an input or an output operand (result) in the execution of most instructions. It consists of 4-bit. Register B Register B is used to store a temporary data in CPU. It consists of 4-bit. Register H Register H is used to indicate an address of the data memory in conjunction with register L. It consists of 1-bit, which is related with the bit 0 of accumulator Register L Register L is used to indicate an address of the data memory in conjunction with register H, Also lower 3-bit can be used to indicate the bit position of the port F. It consists of 4-bit Register Z Register Z is used to select a carrier frequency. The carrier frequency must be selected before Port C data write operation. It consists of 3-bit.
Register Z Carrier frequency Bit 2
0 0 0 0 1 1 1 1
Bit 1
0 0 1 1 0 0 1 1
Bit 0
0 1 0 1 0 1 0 1 F SYS/12, 1/2 duty F SYS/12, 1/3 duty F SYS/12, 1/4 duty F SYS/8, 1/2 duty F SYS/8, 1/4 duty F SYS/11, 4/11 duty No carrier No carrier
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6.9 I /O Ports
Port C/REM Port C/REM is a 1-bit output port, which is related with the bit 3 of accumulator, with CMOS N-channel open drain, which have large current sink capability, for I.R.LED drive. This output can be configured as carrier frequency by programming the register Z and port C data. This pin is put into the high-impedance state in stop mode.
Port D Port D is a 4-bit input port with pull-up resistor. Forcing any input pins to "L" state, system reset occurs and it starts to operate from the reset address.
Port E Port E is a 4-bit input port with pull-up resistor. Forcing any input pins to reset occurs and it starts to operate from the reset address.
Port F Port F is an 8-bit output port with N-channel open drain. Each output which specified by the lower 3-bit of register L can be set and reset individually. All F pins are put into the low state in stop mode.
Port G Port G is a 1-bit output port with N-channel open drain. When stop mode is specified, this pin still remains in the previous state. Set this pin to appropriate state before entering stop mode for visible LED or key scan application.
Port K Port K is a 1-bit output port with N-channel open drain. When stop mode is specified, this pin still remains in the previous state. Set this pin to appropriate state before entering stop mode for visible LED or key scan application.
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6.10 Carrier frequency generator
One of seven carrier frequencies can be selected and transmitted through the C/REM pin by programming the register Z and port C.
Fosc/8 (1/2 duty ) Fosc/8 (1/4 duty ) Fosc/11 (4/11 duty ) Vdd ( No carrier ) Register Z output
MUX VSS 3 /
Fsys
(Fsys/12, 1/2 duty) (Fsys/12, 1/3 duty) (Fsys/12, 1/4 duty) (Fsys/8, 1/2 duty) (Fsys/8, 1/4 duty)
Figure 6-3 PORT C/REM and Carrier Output
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6.11 Watchdog timer (WDT)
The watchdog timer provides the means to return to a reset condition when a system malfunction occurs and the program enters an infinite loop caused by noise or any abnormal state. Also this timer have a function of oscillation stabilization timer. This is a 13-bit counter, counts the clock which is divided twelve (FSYS/12). In the stop mode the oscillation circuit stops but when a key input is detected (Port D, Port E) oscillation starts. When 12288 clock cycles have been counted, the program will be executed from reset address (000H). If the port C data register's value does not change from "L" to "H" before the timer counts 98304 clock cycles, a device reset condition is generated. The oscillator stabilization time : 12/FSYS * 2 10 = 1/FSYS * 12288 = 27mS (@455KHz) The time-out period : 12/FSYS * 213 = 1/FSYS * 98304 = 216mS (@455KHz)
Fsys/12
CLK
Watchdog Timer (13-bit) OPSTART Operating Start OVERFLOW To Reset Logic RESET
Power-on Reset Active Stop Mode Active PORT C Data : Low to High Transition Normal mode OSCOUT 27mS(Min.) PC WDT counting value 98304 Stop mode Normal mode
Watchdog Timer Overflow PORT C Data Low to High STOP Instruction
PORT C Data Low to High 12288 0
Time
Figure 6-4. Function of Watchdog Timer
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6.12 Power-on reset
The SD6830 incorporates an on-chip power-on reset circuitry which provides internal chip reset for most power-up situations. The power-on reset circuit and the watchdog timer are closely related. On power-up the power-on reset circuit is active and watchdog timer is reset. After the reset time, which is in proportion to the rate of rise of VDD, watchdog timer begins counting. After the oscillator stabilization time, which is typically 27mS in FSYS=455KHz, program execution proceeds from reset address (000H).
VDD 7pF
DMC6830 SD6830
VDD 1.8V 0.3VDD
VDD PIN
Internal /POR 2Mohm VSS
Internal /POR
0 RESET TIME
Figure 6-5. Built-in Power-on Reset
6.13 Stop mode
The SD6830 support the stop mode to reduce power consumption. This mode is entered when the STOP instruction is executed during key inputs are not active. Activating any key inputs (Port D, Port E) the device is awakened from stop mode and restarts to operate from reset address. When the device is released from stop mode, following module set to appropriate value in reset routine: PORT G and PORT K. In stop mode, the oscillator is stopped and the each port state is as follows. Port C/REM become inactive state. ( Port G and Port K retain previous state. for including I.R.LED driver,
after the reset release)
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VDD PORT D 4 PORT E 4 STOP instruction internal /POR WDT overflow STOP RESET
SD6830
DMC6830 Key input ( PORT D or PORT E ) Internal /STOP OSCOUT 27mS(Min.) Stop mode Normal mode STOP instruction Stop mode
Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode
6.14 OSC Divide Option
The OSC divide option provides a maximum 1MHz system clock (FSYS). FOSC which is generated in oscillation circuit is divided eight or non-divide to produce F SYS. This dividing ratio will be selected by mask option.
F OSC : Oscillator clock, FSYS : System clock (FOSC or FOSC /8)
MASK OPTION OSC IN OSC OSC OUT FOSC DIVIDE-8 F SYS
Figure 6-7 OSC Divide Option
7. Electrical Specifications 7.1 Absolute maximum ratings
Symbols
VDD VI VO T OPR T STG
Parameters
Supply Voltage Input Voltage Output Voltage Operating temperature Storage Temperature
Conditions
Ta=25E -
Ratings
-0.3 ~ 6.0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 -20 ~ 85 -40 ~ 125
Units
V V V E E
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7.2 Recommended operating conditions
(VDD = 3V 10%, Ta=-20 ~ 70E, unless otherwise noted)
Symbols
VDD VIH1 VIH2 VIL1 VIL2
Parameters
Supply Voltage "H" input Voltage, all input pins except OSCIN "H" input Voltage, OSCIN "L" input Voltage, all input pins except OSCIN "L" input Voltage, OSCIN Oscillating frequency Non-divide option Divide-8 option
Min.
1.8 0.7VDD VDD-0.3 0 0 250 2
Typ.
Max.
3.6
Units
V -V V V V KHz MHz
VDD VDD 0 0
VDD VDD 0.3 VDD 0.3 1000 6
F OSC
7.3 Electrical characteristics
(VDD = 3V 10%, Ta= 25E , unless otherwise noted)
Symbols
VDD IOH IOL0 IOL1 IOL2 IOL3 ILIH1 ILIH2 ILIL ILOH RPULL-UP IDD IDDS F SYS F OSC
Parameters
Supply Voltage "H" output current "L" output current
Test Conditions
250KHzAF OSCA 3.9MHz 3.9MHzAF OSCA 6.0MHz VO = 2.0V, Port C VO = 0.4V, Port C VO = 0.4V, Port C
Min.
1.8 2.2 -6 1.5 180 0.5 1.5 -0.6 30
Typ. Max. Units
3.0 3.0 -9 3 210 1.0 3.0 3 -3 70 0.5 3.6 3.6 -14 4.5 240 2.0 4.5 3 10 -10 1 150 1.0 1.0 1000 1000 6 V V mA mA mA mA mA E E E E KU mA E KHz KHz MHz
"L" output current
VO = 0.4V, Port F VO = 0.4V, Port G/K VI = VDD, Port D/E VI = VDD, OSCIN VI = VSS, OSCIN VO = VDD, Port C/F/G/K VI = 0V, VD D =3V
"H" input leakage current "L" input leakage current "H"output leakage current Pull-up resistance of input Port Supply current at normal mode Supply current at stop mode Clock frequency Oscillator frequency
250 Non-divide option Divide-8 option 250 2
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8. Packing Outlines and Dimensions 24 SOP-300 0.4160(10.566) 0.3980(10.109) 0.2980(7.569) 0.2920(7.417) BASE PLANE SEATING PLANE 0.0118(0.300) 0.0040(0.102) 0.0200(0.508) 0.0138(0.351) 0.0125(0.318) 0.0091(0.231)
45 0.0160(0.406) 0.0100(0.254)
0.6100(15.494) 0.6040(15.342)
0.0500 BSC (1.270)
0.1040(2.642) 0.0940(2.388) UNIT : INCH (MM) 20 SOP-300
0.4160(10.566) 0.3980(10.109) 0.2980(7.569) 0.2920(7.417) 0.0500 BSC 0.0200(0.508) 0.0138(0.351) (1.270)
BASE PLANE SEATING PLANE 0.0118(0.300) 0.0040(0.102) 0.0125(0.318) 0.0091(0.231) 0.5080(12.903) 0.5020(12.751) 45 0.0160(0.406) 0.0100(0.254) 0.0350(0.889) 0.0160(0.406) UNIT : INCH (MM) 0 ~8 0.1040(2.642) 0.0940(2.388)
16
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0.0350(0.889) 0.0160(0.406)
2-EJECTION MARK (OPTION 1)
1.043(26.492) 1.023(25.984)
1.265(32.131) 1.245(31.623) 0.035(0.889) 0.020(0.508)
0.035(0.889) 0.020(0.508)
KSI-W002-000 0.145(3.683) 0.135(3.429) 0.180(4.572) 0.155(3.937) 0.140(3.556) 0.120(3.048) 20 DIP-300 UNIT : INCH (MM) 0.014(0.356) 0.008(0.200)
0.145(3.683) 0.135(3.429) 0.180(4.572) 0.155(3.937)
0.140(3.556) 0.120(3.048)
0 . 0 7 9 ( 2 . 0 0 7 ) 0 . 0 6 5 ( 1 . 6 5 0 0 . 0 2 1 ( 0 . 5 3 30). 1 0 0 B S C ) 0 . 0 5 9 ( 1 . 4 9 9 ) 0 . 0 5 0 ( 1 . 2 7 0 0 . 0 1 5 ( 0 . 3 8 1 )( 2 . 5 4 0 ) )
0.090(2.286) 0.065(1.650) 0.070(1.778) 0.050(1.270)
0.021(0.533) 0.015(0.381)
0.100 BSC (2.540)
0.300 BSC (7.620) 0.270(6.858) 0.250(6.350)
0.300 BSC (7.620) 0.270(6.858) 0.250(6.350)
24 DIP-300
UNIT : INCH (MM)
SD6830
3 ~ 11
3 ~ 11
0.014(0.356) 0.008(0.200)
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9. Instructions 9.1 Symbol Description
SYMBOL
A,B,L H Z PCH PCL PC SK CY SF C, G, K D, E F c M[(HL)] or @HL 4 Bit Register 1-Bit Register 3-Bit Register The Higher 4-Bit of the Program Counter The Lower 6-Bit of the Program Counter 10-Bit Program Counter ( Consisting of the PCH and PCL ) 10-Bit Stack Register 1-Bit Carry Flag 1-Bit Skip Flag 1-Bit Port 4-Bit Port 8-Bit Port Direction of Data Flow The Contents of Data Memory Addressed by Reg HL
DESCRIPTIONS
M[(HL)].b or @HL.b The Specified Bit's Content of Data Memory Addressed by Reg HL @HL+ addr n As a result of execution, increment L by one Address immediate data
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9.2 Opcode Map
MSB 0000b LSB
0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh IFEQU n IFEQU @HL CLRB CY SETB CY CLRB F SETB F STA C IF0 CY RET STA B STA L CLRB G SETB G CLRB K SETB K IF0 @HL.b STA H
0001b 1h
ADDC @HL LDA H LDA E RRC LDA D LDA B LDA L NOT
0010b 2h
XCH @HL+ XCH @HL INC L LDA @HL CLRB H SETB H
0011b 3h
0100b 4h
0101b 5h
0110b 6h
0111b 7h
1000b~ 1100b~ 1011b 1111b 8h~Bh Ch~Fh
0h
NOP STOP
CALL addr
LDZ n
JMPL addr
STA @HL+ STA @HL
LDL n
ADD n
LDA n
JMP addr
CAL addr
CLRB @HL.b
SETB @HL.b
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9.3 Instruction Descriptions
ADD n
Binary code Syntax Operation Flags Words/Cycles Description Example the accumulate.
: 0110xxxx : [] ADD n : (A) c (A) + n, n=0~15 ( n must be decimal number ) : CY: Unaffected. SF: Set to one if carry occurs, cleared otherwise. : 1/1 : Adds an immediate data to the accumulator and stores the result in : ADD 8 JMP 035 JMP 05F ; ; ; Add 8 to A. Jump to 035 if 0AAA7 Jump to 05F if 8AAA15
ADDC @HL Binary code Syntax Operation Flags Words/Cycles Description 00010000 : [] ADDC @HL : (A) c (A) + M[(HL)] + (CY), (CY) c Carry : CY: Set on carry-out of (A) + M[(HL)] + (CY) SF: Unaffected : 1/1 : Adds the contents of the accumulator, the contents of data memory addressed by registers H and L, and the carry bit. It stores the result in the accumulator and the carry flag. Example : CLRB LDA CLRB LDL ADDC CAL addr Binary code Syntax Operation Flags Description : 11xxxxxx : [] CAL addr : (SK1) c (SK0), (SK0) c (PC) + 1, (PCL) c addr, addr = 000 ~ 03F ( addr must be hexadecimal number ) : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 : Calls a subroutine located at the indicated address and pushes the current contents of the program counter to the top of stack. The indicated address must be within the current page. Example : CAL 100 : Call subroutine located at the 100. The 100 must be logical address and within the current page.
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CY 5 H 6
; Clear CY to zero ; Load 5 to A ; Clear H to zero ; Load 6 to L
@HL ; Add the content of A, M[(06)], and the content of CY
SD6830
CALL addr Binary code : 010100xx Syntax Operation Flags : xxxxxxxx
[] CALL addr : (SK1) c (SK0), (SK0) c (PC) + 1, (PC) c addr, addr = 000 ~ 3FF ( addr must be hexadecimal number )
: CY: Unaffected SF: Unaffected
Words/Cycles : 2/2 Description : Calls a subroutine located at the indicated address and pushes the current contents of the program counter to the top of stack. The indicated address can be anywhere in the full 1Kbyte memory space. Example : CALL 2FF ; Call subroutine located at the 2FF. The 2FF must be logical address. CLRB @HL.b Binary code : 010110xx Syntax Operation Flags : [] CLRB @HL.b : M[(HL)].b c 0 : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 Description Example : Clears the specified bit of data memory addressed by registers H and L to zero. : CLRB H LDL CLRB CY Binary code : 00001000 Syntax Operation Flags : [] CLRB CY : (CY) c 0 : CY: Set to zero SF: Unaffected Words/Cycles: 1/1 Description Example : Clears the carry flag to zero. : CLRB CY ; Clear CY to zero 10 CLRB @HL.0 ; Clear H to 0 ; Load 10 to L. The 10 must be decimal number. ; Clear the bit 0 of M[(0A)] to 0.
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CLRB F Binary code Syntax Operation Flags
Words/Cycles
: : : :
:
00001010 [] CLRB F F.(L) c 0 CY: Unaffected 1/1 SF: Unaffected
Description L to zero. Example CLRB CLRB G Binary code Syntax Operation Flags
Words/Cycles
: Clears the specified bit of port F addressed by the lower 3-bit of register : LDL 13 ; Load 13 to L
F
: Clears the bit 5 of F to zero
: 00101100 : [] CLRB G : G.(L) c 0 SF: Unaffected
:
: CY: Unaffected 1/1 CLRB G ; Clear G to zero
Description Example CLRB H Binary code Syntax Operation Flags
Words/Cycles
: Clears the port G to zero. :
: : : :
:
00100100 [] CLRB H (H) c 0 CY: Unaffected SF: Unaffected 1/1 SETB H was used just before.
Description Example
: Clears the contents of register H to zero. Skip this instruction if it or : IFEQU 1 CLRB H SETB H ; Clear H to zero and skip continuous SETB H/CLRB H, if (A)A1 ;
Sets H to one and skip continuous SETB H/CLRB H, if (A)=1
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CLRB K Binary code Syntax Operation Flags
Words/Cycles
: 00101110 : [] CLRB K : (K) c 0 : CY: Unaffected SF: Unaffected
:
1/1 ; Clear K to zero.
Description Example IF0 @HL.b Binary code Syntax Operation Flags
Words/Cycles
: Clears the port K to zero. : CLRB K
: 000001xx : [] IF0 @HL.b : M[(HL)b] = 0 : CY: Unaffected SF: Set to one if equal, cleared otherwise
:
1/1 Compares the specified bit of data memory addressed by registers H ; ; Set H to one Load 4 to L
Description and L with zero. Example
:
: SETB H LDL JMP JMP 4 020 030
IF0 @HL.3 ; Compare the bit 3 of M[(14)] with zero ; Jump to 020 if not equal ; Jump to 030 if equal
IF0 CY Binary code Syntax Operation Flags Words/Cycles Description Example : : : : : :
:
00011100 [] IF0 CY (CY) = 0 CY : 1/1 Compares the carry flag with zero. IF0 CY JMP 030 JMP 040
; Compare the content of CY to zero ; ;
Unaffected
SF : Set to one if equal, cleared otherwise
Jump to 030 if not equal Jump to 040 if equal
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IFEQU @HL Binary code Syntax Operation Flags
Words/Cycles
: : : :
:
00001111 [] IFEQU @HL (A) = M[(HL)] CY : Unaffected SF : Set to one if equal, cleared otherwise 1/1 Compares the contents of accumulator with the contents of data memory addressed by registers H and L. ; ; ; Load 14 to A, and 14 must be decimal number Sets H to one Loads 4 to L LDA SETB LDL 4 14 H
Description Example
: :
IFEQU @HL ; Compares 14 with M[(14)] JMP 050 JMP 060 IFEQU n Binary code Syntax Operation Flags
Words/Cycles
; Jump to 050 if not equal ; Jump to 060 if equal 0111xxxx
: : : :
:
00001110 [] IFEQU n
(A) = n, n = 0 ~15 ( n must be decimal number ) CY: Unaffected SF: Set to one if equal, cleared otherwise
2/2
Description Example
: Compares the contents of accumulator with an immediate data. : IFEQU 15 JMP JMP 070 080 ; Compare the contents of accumulator with 15 ; Jump to 070 if not equal ; Jump to 080 if equal
INC L Binary code Syntax Operation Flags
Words/Cycles
: : : :
:
00100010 [] INC L (L) c (L) + 1 CY : Unaffect
1/1
SF:As a result of execution, set to one if the contents of register L are zero, cleared otherwise.
Description Example
: :
The contents of register L are incremented by one. LDL INC INC JMP JMP 14 L L 0A0 ; ; ; Load 14 to L The contents of L are incremented by one The contents of L are incremented by one ; Jump to 0A0
KSI-W002-000 24
090 ; It is skipped because the contents of L is
SD6830
JMP addr Binary code Syntax Operation Flags
Words/Cycles
: 10xxxxxx : [] JMP addr : (PCL) c addr, addr = 00 ~ 3F ( addr must be hexadecimal number ) : CY : Unaffected SF : Unaffected
: 1/1
Description Example
: Jumps unconditionally to the indicated address. The indicated address must be within the current page. : JMP 2EF ; Jump unconditionally to the 2EF. The 2EF address must be within the current page.
JMPL addr Binary code Syntax Operation Flags : 010101xx xxxxxxxx : [] JMPL addr : (PC) c addr, addr = 000 ~ 3FF (addr must be hexadecimal number. ) : CY : Unaffected SF : Unaffected Words/Cycles : 2/2 Description Example LDA @HL Binary code Syntax Operation Flags : 00100011 : [] LDA @HL : (A) c M[(HL)] : CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description Example : Loads the contents of memory addressed by registers H and L into the accumulator. : SETB LDL LDA H 0 ; ; Set H to 1 Load 0 to L Load M[(10)] into A : Jumps unconditionally to the indicated address. The indicated address can be anywhere in the full 1K-byte memory space. : JMPL 100 ; Jump unconditionally to 100
@HL ;
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SD6830
LDA n Binary code : Syntax Operation Flags : : 0111xxxx (A) c n, n=0~15 ( n must be decimal number. ) CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description Example : Loads an immediate data into the accumulator. Skip this instruction if it was used just before. : STA LDA LDA LDA JMP LDA B Binary code : Syntax Operation Flags : : 00010101 [] LDA B (A) c (B) SF : Unaffected Words/Cycles : 1/1 Description Example LDA D Binary code : 00010100 Syntax Operation Flags : : : [] LDA D (A) c (D) CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description Example : Loads the contents of port D into the accumulator. : LDA D ; Load the contents of D into A : Loads the contents of register B into the accumulator. : LDA B ; Load the contents of B into A B 15 4 7 0B0 ; Load 15 into A. ; ; It is skipped because this instruction was used just before It is skipped because this instruction was used just before : [] LDA n
; Jump to 0B0
: CY : Unaffected
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SD6830
LDA E Binary code Syntax Operation Flags Words/Cycles Description Example : : : 00010010 [] LDA E (A) c (E) SF : Unaffected
:
: CY : Unaffected 1/1. E ; Load the contents of E into A
: Loads the contents of port E into the accumulator : LDA
LDA H Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
00010001 [] LDA H (A) c (H) CY : Unaffected SF : Unaffected 1/1
: Loads the contents of register H into the bit 0 of accumulator. : LDA H ; Load the content of H into the bit 0 of A
LDA L Binary code : Syntax Operation Flags : : : 00010110 [] LDA L (A) c (L) CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description Example : Loads the contents of register L into the accumulator. : LDA L ; Load the contents of L into A
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SD6830
LDL n Binary code : 0100xxxx Syntax Operation Flags : : : [] LDL n (A) c n, n = 0 ~ 15 ( n must be decimal number ) CY : Unaffected SF : Unaffected Words/Cycles : 1/1 Description Example : Loads an immediate data to the register L. Skip this instruction if it was used just before. : LDA LDL LDL 3 8 4 ; Load 8 to L ; It is skipped because this instruction was used just before ; Jump to 0C0
JMP 0C0 LDZ n Binary code Syntax Operation Flags Words/Cycles Description Example NOP Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
: : : :
:
00110xxx [] LDZ n (A) c n, n = 0 ~ 7 ( n must be decimal number ) CY : Unaffected SF : Unaffected 1/1 Load an immediate data into the register Z. LDZ 0 ; Load 0 into Z. The 0 must be decimal number
: :
00000000 [] NOP (PC) c (PC) + 1 CY : Unaffected SF : Unaffected 1/1 No operation. NOP ; No operation
: :
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SD6830
NOT Binary code Syntax Operation Flags : : : : 00010111 [] NOT (A) c /(A) CY : Unaffected SF : Unaffected Words/Cycles : Description Example : : 1/1 The contents of accumulator are 1 LDA 7 NOT RET Binary code Syntax Operation Flags : 00011101 : [] RET : (PC) c (SK0), (SK0) c (SK1) : CY: Unaffected SF: Unaffected Words/Cycles : 1/1 Description Example RRC Binary code Syntax Operation Flags : 00010011 : [] RRC : (A.b) c (A.b+1) (A.3) c (CY) (CY) c (A.0) : CY : Set to bit 0 of the accumulator SF : Unaffected Words/Cycles : 1/1 Description : Shifts the contents of accumulator 1-bit to the right through the carry. The carry bit content shifts into the bit 3 of accumulator, and the bit 0 of accumulator is shifted into the carry bit. Example : SETB CY ; Set CY to one. LDA RRC 5 ; Load 5 to A ; CY becomes zero, and the contents of A is 11 : : Returns from the subroutine to main routine. RET ; Returns from the subroutine to main routine ; 1's complement 7, then leaves 8 in A
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SD6830
SETB @HL.b Binary code Syntax Operation Flags Words/Cycles Description Example : 010111xx : [] SETB @HL.b : :
:
M[(HL)].b c 1 CY : Unaffected SF : Unaffected 1/1 CLRB H LDL 5 SETB @HL.2 ; Clear H to zero ; Load 5 to L ; Set the bit 2 of M[(05)] to one
: Sets the specified bit of memory addressed by registers H and L to one. :
SETB CY Binary code Syntax Operation Flags Words/Cycles Description Example SETB F Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
: : : :
:
00001001 [] SETB CY (CY) c 1 CY : Set to one SF : Unaffected 1/1 Sets the contents of carry flag to one. SETB CY ; Sets the content of CY to one
: :
00001011 [] SETB F F.(L) c 1 CY : Unaffected SF : Unaffected 1/1 Sets the specified bit of the port F addressed by register L to one. LDL 4 SETB F ; Loads 4 to L ; Sets the bit 4 of F to one
: :
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SD6830
SETB G Binary code Syntax Operation Flags Words/Cycles Description Example SETB H Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
: : : :
:
00101101 [] SETB G (G) c 1 CY : Unaffected SF : Unaffected 1/1 Sets the port G to one. SETB G ; Sets the port G to one
: :
00100101 [] SETB H (H) c 1 CY : Unaffected SF : Unaffected 1/1 Sets the contents of register H to one. Skip this instruction if it or SETB H was used just before. : IFEQU 1 SETB H ; Sets H to one and skip continuous CLRB H/SETB H, if (A)A1 CLRB H ; Clear H to zero and skip continuous CLRB H/SETB H, if (A)=1
:
SETB K Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
00101111 [] SETB K (K) c 1 CY : Unaffected SF : Unaffected 1/1 Sets the port K to one. SETB K ; Sets the port K to one
: :
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SD6830
STA @HL Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
00101001 [] STA @HL M[(HL)] c (A) CY : Unaffected SF : Unaffected 1/1 Stores the contents of accumulator in memory addressed by registers H and L. : LDL SETB STA 0 H ; Load 0 to L ; Set H to one
:
@HL ; Stores the contents of A in M[(10)]
STA @HL+ Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
00101000 [] STA @HL+ M[(HL)] c (A), (L) c (L) + 1 CY : Unaffected SF : Unaffected 1/1 Stores the contents of accumulator in memory addressed by registers H and L. And then the contents of register L are incremented by one. LDL SETB STA JMP JMP 15 H @HL+ 035 045 ; Load 15 to L ; ; Set H to one It is skipped because L is "0" ; Stores the contents of A in M[(1F)]. L becomes ; Jump to 045
: :
STA B Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
00011110 [] STA B (B) c (A) CY : Unaffected SF : Unaffected 1/1 Stores the contents of accumulator in the register B. STA B ; Stores the contents of A in B
KSI-W002-000 32
: :
SD6830
STA C Binary code Syntax Operation Flags Words/Cycles Description Example STA H Binary code Syntax Operation Flags Words/Cycles Description Example STA L Binary code Syntax Operation Flags Words/Cycles Description Example : : : :
:
: : : :
:
00001100 [] STA C (C) c (A)3 CY : Unaffected SF : Unaffected 1/1 Stores the bit 3 of accumulator in the port C. STA C; Stores the bit 3 of A in C
: :
: : : :
:
00000011 [] STA H (H) c (A)0 CY : Unaffected SF : Unaffected 1/1 Stores the bit 0 of accumulator in the register H. STA H ; Store the bit 0 of A in H
: :
00011111 [] STA L (L) c (A) CY : Unaffected SF : Unaffected 1/1 Stores the contents of accumulator in the register L. STA L ; Stores the contents of A in L
: :
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STOP Binary code Syntax Operation Flags Words/Cycles Description Example XCH @HL Binary code Syntax Operation Flags Words/Cycles Description : : : :
:
SD6830
: : : :
:
00000001 [] STOP Stop the oscillation of the oscillator, and reset PORT F to zero CY : Unaffected 1/1 Stops the oscillation of the oscillator. STOP 00100001 [] XCH @HL (A) e M[(H,L)] CY : Unaffected SF : Unaffected 1/1 Exchanges the accumulator with the contents of the data memory addressed by registers H and L without going through an intermediate location. SF : Unaffected
: :
:
Example
: LDL SETB XCH
3 H
;
Load 3 to L
; Set H to one going through an intermediate location
@HL ; Exchanges the contents of A with M[(13)] without
XCH @HL+ Binary code Syntax Operation Flags : : : : 00100000 [] XCH @HL+ (A) e M[(H,L)], (L) c (L) + 1 CY : Unaffected SF: As a result of execution, set to one if the contents of register L are zero, cleared otherwise Words/Cycles Description
:
1/1 Exchanges the accumulator with the contents of the data memory addressed by registers H and L without going through an intermediate location. As a result of execution, the contents of register L are incremented by one.
:
Example
:
SETB LDL
H 15
; ; Load 15 into L ; Exchanges A with M[(1F)] without going through an intermediate location. As a result of execution, the contents of L are "0"
CH @HL+
JMP JMP
055 065
; It is skipped because L is "0" ; Jump to 065
KSI-W002-000 34

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